In the field of semiconductor technology, the electrostatic discharge (ESD) phenomenon poses a major threat to the reliability of an integrated circuit (IC) device. As advances in integrated circuit technology enable the decrease in the feature size of circuit elements, the design of reliable ESD protection has become a more difficult and more challenging task in nanoscale CMOS technology.
Silicon-controlled rectifier (SCR) devices are widely used as on-chip electrostatic discharge (ESD) protection due to their ESD robustness and the high current discharge capacity per unit area. When an SCR device is used in an integrated circuit device having a low supply voltage, the high triggering voltage of the SCR device may limit its range of applications. Therefore, some advanced techniques, such as low-voltage triggered SCR (“LVTSCR) have been proposed to improve the triggering efficiency of the SCR device. However, conventional low-voltage triggered SCR devices face the problems of high leakage current and large silicon area.
FIG. 1A illustrates a cross-sectional view of a conventional low-voltage triggered SCR device 10 formed on a P-type substrate 100. The SCR device 10 includes an N-well and a P-well abut one another and formed in the substrate 100. An N+ region 111 and a P+ region 101 are formed in the N-well, and an N+ region 102 and a P-well 112 are formed in the P-well. An additional N+ doped region 103 is formed in a region between the P+ doped region 101 and the N+ doped region 102. A portion of the N+ doped region 103 is disposed in the P-well, and a portion of the N+ doped region is disposed in the N-well. A gate structure 104 is formed on the semiconductor substrate 100 between the N+ doped region 102 and the N+ doped region 103. The gate structure 104 is connected to a cathode of the SCR device to form a gate-grounded NMOS transistor.
FIG. 1B illustrates a schematic circuit with an SCR 10′. As shown in FIG. 1B, the SCR 10′ is connected between an anode and a cathode. The SCR 10′ includes a PNP transistor, an NPN transistor, an NMOS transistor, a resistor RNW, and a resistor RPW. The PNP transistor has an emitter connected to the anode, a base connected to the drain of the NMOS transistor, and a collector connected to a source of the NMOS transistor and a base of the NPN transistor. The resistor RNW is connected between the anode and a drain of the NMOS transistor.
Referring to FIGS. 1A and 1B, the resistor RNW is substantially formed in the N-well, and the resistor RPW is substantially formed in the P-well. The P+ region 101, the N-well and the P-well form the PNP transistor. The N+ region 102, the P-well and the N-well form the NPN transistor.
When an ESD event occurs at the anode of the SCR device, the NMOS transistor turns on causing a current to flow through the resistor RPW. The voltage drop across the resistor RPW turns on the bipolar NPN transistor and ultimately triggers the SCR device. The NMOS thus, reduces the trigger voltage of the SCR device. However, the sustaining voltage of the low trigger voltage SCR device is relatively low, so that when the SCR device is applied to a 3.3 V or 5 V I/O (input/output), the low sustaining voltage causes the SCR device to latch-up. This is because, when the SCR device is operating properly, the low sustaining voltage enables the SCR device to remain active (i.e., in the on state) in a low-impedance state even after the ESD event has passed. This effect is referred to as an ESD induced latch-up. Furthermore, the additional N+ region 103 disposed between the N-well and the P-well increases the silicon area.
Thus, there is a need to provide a novel silicon controlled rectifier structure to overcome the above-described deficiencies.